The present invention relates to an image sensor; and, more particularly, to a CMOS image sensor integrated with a photodiode and a method for fabricating the same, which is capable of improving a charge capacity and an optical sensitivity thereof.
As is well known, an image sensor is an apparatus for sensing a light reflected from an object and generating an image data. Especially, an image sensor fabricated by using a CMOS (complementary metal oxide semiconductor) technology is called a CMOS image sensor.
Generally, the CMOS image sensor includes a plurality of unit pixels having a light sensing region and a peripheral circuit region. Each of the unit pixels also includes a light sensing element formed on the light sensing region and a plurality of transistors formed on the peripheral circuit region. The light sensing element such as a photodiode senses incident light reflected from an object, to accumulate photoelectric charges that are generated due to an incident light. The transistors control a transfer of the photoelectric charges.
FIG. 1 is a diagram showing a layout of a unit pixel contained in a conventional CMOS image sensor. Reference numerals 102 and 104 represent gate electrodes for transistors, 103 a floating diffusion region, and 105 an isolation region. A reference numeral 106 represents a light sensing region and a reference numeral 107 represents a semiconductor substrate. FIGS. 2A to 2D are cross-sectional views, taken along the line A-Axe2x80x2, showing sequential steps for fabricating a conventional unit pixel.
Hereinafter, a method for fabricating a conventional unit pixel with reference to FIG. 1 and FIGS. 2A to 2D.
As shown in FIG. 2A, a P-type epitaxial layer 20 is grown on a P-type substrate (not shown). Patterned field oxide layers 30, patterned gate oxide layers 40, and gate electrodes 50 are sequentially formed on a peripheral circuit region 11 of the P-type epitaxial layer 20, to thereby provide a semiconductor structure.
As shown in FIG. 2B, after forming mask patterns 60A on the semiconductor structure, a low-concentration and high-energy ion implantation is performed to form an N-type doping region 70, on a portion to be a light sensing region 10. At this time, referring to FIG. 1, the mask patterns 60A are designed to cover a portion of the light sensing region 106, not to expose an entire light sensing region 106. Furthermore, the mask patterns 50A are designed to expose a portion of the gate electrode 104.
As shown in FIG. 2C, the mask patterns 60A are removed and another mask patterns 60B are formed. Then, a high-concentration and low-energy ion implantation is performed to form a P-type doping region 80 beneath a surface of P-type epitaxial layer 20. At this time, referring to FIG. 1, the mask patterns 60B are designed to expose the entire light sensing region 106 and to expose a portion of the gate electrode 104.
As shown in FIG. 2D, spacers 90 and source/drain junction regions 100 are formed on the peripheral circuit region 11.
As can be seen, a conventional photodiode has a PNP structure, which is constituted with the P-epitaxial layer 20, the N-type doping region 70 and the P-type doping region 80. The N-type doping region 70 plays a role of a depletion layer for accumulating photoelectric charges that are generated due to the incident light. Also, the N-type doping region 70 can be fully depleted due to the P-type doping region 80.
However, in case where the incident light is a blue light having a short wavelength, the incident can not be transmitted deeply up to the P-type epitaxial layer 20. Therefore, the photoelectric charges are generated at a surface of the photodiode. At this time, the photoelectric charges are decreased due to the existence of the P-type doping region 80, so that the optical sensitivity is relatively degraded.
Furthermore, since the P-type doping region 80 is aligned at the edges of the gate electrodes 204 by the ion implantation, dopants of the P-type doping region 80 are diffused to channel regions of the transistors at a following thermal treatment process. As a result, a high potential barrier is caused, and charge transfer efficiency representing a rate of the photoelectric charges transferred to the floating diffusion region 103 is decreased.
It is, therefore, an object of the present invention to provide a CMOS image sensor integrated with a photodiode and a method for fabricating the same, which is capable of improving a charge capacity and an optical sensitivity thereof.
In accordance with an aspect of the present invention, there is provided a CMOS image sensor containing a plurality of unit pixels, each unit pixel having a light sensing region and a peripheral circuit region, comprising: a semiconductor substrate of a first conductive type; a transistor formed on the peripheral circuit region of the semiconductor substrate, wherein the transistor has a gate oxide layer and a gate electrode formed on the gate oxide layer; spacers formed on sidewalls of the gate oxide layer and the gate electrode, wherein one spacer are formed on the light sensing region; a first doping region of a second conductive type formed on the light sensing region, wherein the first doping region is extended to an edge of the gate electrode; and a second doping region of the first conductive type formed on the first doping region, wherein the second doping region is extended to an edge of a spacer formed on the light sensing region.
In accordance with another aspect of the present invention, there is provided a 7. A method for fabricating a CMOS image sensor having a plurality of unit pixels, each-unit pixel having a light sensing region and a peripheral circuit region, comprising the steps of: a) providing a semiconductor substrate of the first conductive type; b) sequentially forming a gate oxide layer and a gate electrode on the peripheral circuit region of the semiconductor substrate; c) forming a first doping region of a second conductive type on the light sensing region of the semiconductor substrate, wherein the first doping region is extended to an edge of the gate electrode; d) forming spacers on sidewalls of the gate oxide layer and the gate electrode, wherein one spacer is formed on the light sensing region; and e) performing an ion implantation to form a second doping region of the first conductive type, wherein the second doping region is extended to an edge of a spacer formed on the light sensing region.